BIOS 개발전문회사 Xannex Technologies


  Intel Queens Bay Platform


인텔® 아톰™ 프로세서 E6xx 시리즈(인텔® 플랫폼 컨트롤러 허브 EG20T 포함)
Queens Bay (Tunnel Creek + Topcliff)



☞ 사양
인텔® 아톰™ 프로세서 E6xx 시리즈는 FSB(Front-side bus) 및 DMI(Direct Media Interface)와 같은 독점 인터페이스를 사용하지 않고 프로세서 대 칩셋 인터페이스의 표준인 공개형 PCI-Express*로 옮겨감으로써 탁월한 I/O 유연성을 제공합니다. 집적도가 높은 프로세서는 3D 그래픽과 비디오 인코딩/디코딩 그리고 메모리 및 디스플레이 컨트롤러를 하나의 패키지에 통합하고 있어 재료비를 절감하고 보드 크기를 줄이는 데 도움이 됩니다.

이 릴리스의 프로세서는 산업 자동화, 소매, 게임 및 디지털 신호와 같은 다양한 시장 부문에서 인텔® 플랫폼 컨트롤러 허브 EG20T와 함께 사용하거나 차량 내 인포테인먼트 시스템, 미디어 전화기, 커넥티드 서비스 게이트웨이 등 많은 임베디드 분야의 특정 I/O 요구 사항에 맞도록 다양한 타사 공급업체(OKI Semiconductor Co. Ltd., Realtek Semiconductor Corp., STMicroelectronics 포함)의 I/O 허브와 함께 사용할 수 있습니다. 최소한의 I/O 인터페이스가 요구되는 분야의 개발자들은 I/O 허브 대신 PCIe-GbE 컨트롤러 또는 PCIe-SATA 컨트롤러 같은 이산 PCIe* 장치를 사용할 수도 있습니다.

인텔® 아톰™ 프로세서 E6xx 시리즈는 산업 및 상업 온도 범위에서 사용할 수 있습니다. 인텔® 프로세서와 플랫폼 컨트롤러 허브 모두 임베디드 라이프사이클 지원을 제공하며 다양한 소프트웨어 요소의 지원을 받습니다.


☞  플랫폼 하이라이트
•Open PCIe* 인터커넥트를 사용하면 인텔 또는 타사 공급업체의 I/O 허브를 선택할 수 있습니다.
•그래픽 및 메모리 컨트롤러와 핵심 오디오, 비디오 인코딩/디코딩 기능을 프로세서에 통합합니다.
•향상된 성능과 멀티 스레드 분야를 제공하기 위해 인텔® 하이퍼 스레딩 기술¹을 지원합니다.
•여러 환경을 하드웨어 플랫폼에 통합함으로써 유연성을 높이고 시스템 활용도를 극대화하기 위해 인텔® 가상화 기술²을 지원합니다.
•차량 내 인포테인먼트 시스템, 산업 제어 및 자동화 분야와 같은 비구속 열 환경을 위한 산업 온도 범위 옵션에서 사용이 가능합니다.


임베디드 컴퓨팅용 인텔® 아톰™ 프로세서 E6xx 시리즈
프로세서전력(TDP)캐시, 코어 GHz인텔 제품 기술
인텔® 아톰™ 프로세서 E6202.7 W512 KB, 0.6 GHz인텔® 하이퍼 스레딩 기술 및 인텔® 가상화 기술
인텔® 아톰™ 프로세서 E620T2.7 W512 KB, 0.6 GHz인텔® 하이퍼 스레딩 기술 및 인텔® 가상화 기술
인텔® 아톰™ 프로세서 E6403.3 W512 KB, 1 GHz인텔® 하이퍼 스레딩 기술 및 인텔® 가상화 기술
인텔® 아톰™ 프로세서 E640T3.3 W512 KB, 1 GHz인텔® 하이퍼 스레딩 기술 및 인텔® 가상화 기술
인텔® 아톰™ 프로세서 E6603.3 W512 KB, 1.3 GHz인텔® 하이퍼 스레딩 기술 및 인텔® 가상화 기술
인텔® 아톰™ 프로세서 E660T3.3 W512 KB, 1.3 GHz인텔® 하이퍼 스레딩 기술 및 인텔® 가상화 기술
인텔® 아톰™ 프로세서 E6803.9 W512 KB, 1.6 GHz인텔® 하이퍼 스레딩 기술 및 인텔® 가상화 기술
인텔® 아톰™ 프로세서 E680T3.9 W512 KB, 1.6 GHz인텔® 하이퍼 스레딩 기술 및 인텔® 가상화 기술

임베디드 컴퓨팅용 인텔® 플랫폼 컨트롤러 허브 EG20T
제품 이름제품 코드전력패키지기능
임베디드 컴퓨팅용 인텔® 플랫폼 컨트롤러 허브 EG20TCS82TPCF1.55WPBGA 23x23mmSATA, USB, SD/SDIO/MMC, 기가비트 이더넷 MAC, CAN, IEEE* 1588, SPI, I2C, UART 및 GPIO를 포함한 다양한 I/O를 지원합니다


☞ Atom Processor E6xx Series Features
■  Low-Power Intel®Architecture Core
• 600 MHz (Ultra Low Power SKU), 1.0 GHz (Mainstream SKU) and 1.3 GHz (Premium SKU)
• Macro-operation execution support
• 2-wide instruction decode and in-order execution
• On die, 32KB 4-way L1 Instruction Cache and 24KB 6-way L1 Data Cache
• On die, 512KB, 8-way L2 cache
• L2 Dynamic Cache Sizing
• 32-bit physical address, 48-bit linear address size support
• Support for IA 32-bit architecture
• Supports Intel® Virtualization Technology (Intel® VT-x)
• Supports Intel® Hyper-Threading Technologyα — two threads
• Advanced power management features including Enhanced Intel SpeedStep® Technology
• Intel® Deep Power Down Technology (C6)
• Intel® Streaming SIMD Extension 2 and 3 (Intel® SSE2 and Intel® SSE3) and Supplemental Streaming SIMD Extensions 3 (SSSE3) support
■  System Memory Controller
• Single-channel DDR2 memory controller
• 32-bit data bus
• Supports DDR2 667 MT/s (Ultra Low Power and Mainstream SKU) and 800 MT/s (Premium SKU) data rates
• Supports 1 or 2 ranks
• Supports x8 or x16 DRAM chips
• One rank - two x16 or four x8 DRAM chips
• Two ranks - two x16 DRAM chips per rank, or four x8 DRAM chips per rank
• Supports up to 1GB of extended memory
• Supports total memory size of 128 MB, 256 MB, 512 MB, and 1 GB
• Supports 256 Mb, 512 Mb, 1 Gb and 2 Gb chip densities for the x8 DRAM
• Supports 512 Mb, 1 Gb and 2 Gb chip densities for the x16 DRAM
• Aggressive power management to reduce power consumption, including shallow self-refresh and a new deep self-refresh support
• Proactive page closing policies to close unused pages
• Supports partial writes through data mask pins
• Supports only soldered-down DRAM configurations. The memory controller does not support SODIMM or any type of DIMMs.
■  Graphics
• Integrated 2D/3D graphic engine
• Supports Video Decode : MPEG2, MPEG4, VC1, WMV9, H.264 (main and high-profile level 4.0/4.1), and DivX*
• Supports Video Encode : MPEG4, H.263, H.264 (baseline@L3), and VGA/QGA
■  Display Interfaces
• LVDS Interface : Maximum resolution up to 1280x768 @ 60Hz
• Serial DVO (SDVO) Display Interface : Maximum resolution up to 1280x1024 @ 85Hz
■  PCI Express*
• 4 x1 lane PCI Express* (PCIe*) root ports
• 4 x1 PCIe* ports
■  Low Pin Count (LPC) 1.1 Interface
■  Intel® High Definition Audio (Intel® HD Audio) Controller
■  System Management Bus (SMBus 2.0)
■  14 GPIOs
■  Serial Peripheral Interface (SPI)
■  Power Management
• Full support for the ACPI 3.0
• Suspend-to-RAM
• Suspend-to-Disk
• Hardware-based thermal management circuit
■  Watchdog Timer (WDT)
■  Real Time Clock (RTC)
■  676-Ball FCBGA package
• Dimensions of 22 mm x 22 mm

☞ Topcliff PCH Overview
• Peripheral Component Interconnect (PCI)-Express*
— Fully compliant with all the required features of the PCI Express* 1.1
    (2.5Gbps) specification. It is used to connect to the Tunnel Creek Processor.
— Supports one PCI Express port with x1 link width
— Supports ultra low transmit and receive latency and high accessible bandwidth
— Supports polarity inversion
— Max Transaction Layer Packet (TLP) payload size is 128 bytes
• Universal Serial Bus (USB) Host
— Supports 6 ports (2 USB 2.0 Hosts; 3 ports for each host)
— Conforms to Extended Host Controller Interface (EHCI) (1.0) and Open Host Controller Interface (OHCI) (1.0a)
— Provides USB port that supports high-speed (480 Mbps), full-speed (12 MBPS), and low-speed (1.5 MBps) operations
— Supports four types of data transfer: Control transfer, Bulk transfer, Interrupt transfer, and Isochronous transfer
— Direct Memory Controller (DMA) controller is built in the host controller
• Universal Serial Bus (USB) Device
— Supports 1 port (1 USB device controller with 1 port)
— Complies with USB 2.0 and USB 1.1 protocols
— Supports high-speed (480 MHz), and full-speed (12 MHz) operations
— Supports up to 4 IN and 4 OUT physical endpoints (EP0-3), which can be tied to different interfaces and configurations to achieve logical endpoints
• Gigabit Ethernet Media Access Controller (GbE MAC)
— Conforms to IEEE802.3
— Supports the Auto CRC adding function and the CRC check function
— Supports the Auto Padding function and the Padding remove function
— Supports the Collision detect function
— Supports the Burst transfer function in the half-duplex mode
— Supports the Auto Extension function in the half-duplex mode
— Provides Media Independent Interface (MII) interface (10/100 BASE) and Reduced Gigabit Media Independent Interface (RGMII) or Gigabit Media Independent Interface (GMII) interface (1000 BASE)
— Supports the Auto transmission stop function at pause packet reception
— Supports the Pause packet transmission function
— Supports the DMA function
• Serial Advanced Technology Attachment (SATA)
— Supports SATA 1.5 Gbps Generation 1 speed and 3 Gbps Generation 2 speed
— Supports 2 ports (2 ports with 1 AHCI SATA Controller)
— Compliant with Serial ATA Specification 2.6, and AHCI Revision 1.1 specifications
— Provides Internal DMA engine
• Secure Digital (SD) Host Controller
— Conforms to Secure Digital Host Controller (SDHC) speed class 6
— Supports 2 ports (2 SD Host Controllers; 1 port for each host)
— Supports the DMA function
— Supports Secure Digital Association (SDA) standard (Conforms to SD Host Controller Standard Specification ver. 1.0)
— Supports the following specifications:
— SD memory card: SD Memory Card Specifications Part 1 Physical Layer Specification ver. 2.0
— SDIO card: SDIO Card Specification ver. 1.10
— MMC: MMC System Specification ver. 4.1
— Supports the following transfer modes:
— SD memory card/SDIO card
— SD bus transfer mode (1-bit/4-bit/high-speed)
— MMC transfer mode (1-bit/4-bit/8-bit/high-speed)
— Supports the following SD option functions:
— Enable block stop, automatic clock stop, Auto_CMD12
— Supports the following SDIO option functions:
— Suspend, resume, wake-up, read wait
• IEEE-1588 (Clock Synchronization)
— Provides the hardware assist logic for achieving precision clock synchronization
— Conforms with the IEEE1588-2008 standard
— Supports IEEE1588 over Ethernet (Interface is MII, GMII or RGMII)
— Supports IEEE1588 over CAN
• Serial Peripheral Interface (SPI)
— Supports up to 5 Mbps
— Performs full-duplex data transfer
— Operates as master mode or slave mode
— Supports the Bus-master function (includes a shared DMA)
— Provides 16-stage FIFOs on the transmit side and the receive side
— Allows selection of 8-bit or 16-bit transfer size
— Allows interrupts to be set within a range of 1 to 16 according to the number of received bytes (words) and the number of not transmitted bytes (words)
— Allows selection of either LSB first or MSB first
— Allows selection of the polarity and phase of the serial clock
— Allows selection of synchronous clocks obtained by dividing the internal-clock
    (50MHz=CLKL) by 2 and up to 2046 (1023 types)
— Allows control of the interval before and after transfer
— Indicates completion of transmission/reception and FIFO status with status bits
— Allows detection of a mode fault error to prevent multi-master bus contention
— Allows detection of a write overflow error that occurs when data is written further in the transmit FIFO full state
— Generates interrupts to handle various situations such as specific states of the transmit/receive FIFOs and mode fault errors
• Controller Area Network (CAN)
— Supports CAN Protocol version 2.0B Active
— No support for Bus-master function (Does not include a local DMA)
— Supports bit rate up to 1 Mbit/s
— Supports 32 message objects
— Each message object has its own identifier mask.
— Each message object has its own direction mask.
— Each message object has its own extended mask.
— Each message object has its own NewDat mask.
— Supports priority control by each message object
— Provides programmable FIFO mode (concatenation of message objects)
— Supports detection/identification of bit error, stuff error, CRC error, form error, or acknowledge error
— Supports Programmable loop-back mode for self-test operation
— Supports DAR (Disabled Automatic Retransmission) mode for time triggered CAN applications
• Inter – Integrated Circuit (I2C) bus controller
— Philips I2C bus specification ver 2.1 conformed controller
— Does not support for Bus-master function (Does not include a local DMA)
— Supports multi-master mode
— Supports the following Data transfer modes:
— Standard mode (100 kHz)
— Fast mode (400 kHz)
— Compatible with 7-bit/10-bit address
— Stops clocks to synchronize data between master and slave
— The I2C processing supports both transmitter and receiver functions (data width is 16 bits).
— The I2C transmitter supports master and slave devices. Also, the I2C receiver supports master and slave devices (selected by setting).
• Universal Asynchronous Receiver-Transmitter (UART) (8-wire interface)
— Supports 1 port
— Interoperable with 16550
— Supports for Bus-master function (includes a shared DMA)
— Provides Full-duplex buffer system
— Supports all status report functions
— Supports reduced interrupts to processor because of the use of 256-byte transmit and receive FIFOs
— Provides transmit, receive, and line-state data set interrupts and independent control of FIFO
— Modem control signals are configured with CTS (Clear To Send), RTS (Request To Send), DSR (Data Set Ready), DTR (Data Terminal Ready), RI (Ring Indicator), and DCD (Data Carrier Detect)
— Supports the following programmable serial interface characteristics:
    — 5, 6, 7 or 8-bit per character
    — Odd parity, even parity, and no-parity generation and verification
    — 1, 1.5 or 2 stop bits
— Supports programmable baud rate generator (max baud rate: 4 Mbps)
• Universal Asynchronous Receiver Transmitter (UART) (2-wire interface)
— Supports 3 ports
— Interoperable with 16550
— Supports for Bus-master function (includes a shared DMA)
— Supports Full-duplex buffer system
— Provides all status report functions
— Supports reduced interrupts to MPU because of the use of 64-byte transmit and receive FIFOs
— Provides transmit, receive, and line-state data set interrupts and independent control of FIFO
— Supports the following programmable serial interface characteristics
— 5,6,7 or 8-bit per character
— Odd parity, even parity, and no-parity generation and verification
— 1 or 1.5 or 2 stop bits
— Supports programmable baud rate generator (max baud rate: 921.6 Kbps)
• GPIO
— 12–bit General purpose 12 GPIO ports.
— Input or output can be specified for each port.
— Interrupts can be used for all of the bits.
— Interrupt mask and interrupt mode (level/edge, positive logic/negative logic) can be set for all bits.
— GPIO0-7 correspond to WAKE-ON (GPIO8-11 does not correspond)
• JTAG
— Supports Boundary SCAN mode
— Supports Internal signal monitor mode
— Supports E-Fuse write mode
• Serial ROM I/F
— Supports access to the Option ROM of each function
— Loading of a parameter required for initialization of each function (GbE MAC and SATA AHCI initialization).
— SPI interface.


☞  Product Brief: Intel® Atom™ Processor E6xx Series with Intel® Platform Controller Hub EG20T for Embedded Computing



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